The present invention relates to an output circuit.
In circuits where it is desired to combine together two clocked outputs from respective clocked logic circuits into a single clocked output, production of the final output may need to be delayed to allow the outputs of the clocked logic circuits to settle. This can be disadvantageous in that the time available for a downstream circuit to respond is restricted by such a delay. It may be possible to overcome this difficulty by ensuring that downstream circuitry is fast responding but this in itself has a cost disadvantage since fast circuits are normally more expensive. This is especially true where the downstream circuitry is a semiconductor memory.
It is accordingly an object of the present invention to at least partially mitigate the difficulties of the prior art.
According to a first aspect of the present invention there is provided an output circuit comprising a two input multiplexer having a clock terminal, a flip-flop coupled to one of the multiplexer inputs and a clocked latch coupled to the other of the multiplexer inputs, wherein said flip-flop and said clocked latch each have a clock input and said clock terminal of said multiplexer and said clock inputs of said flip-flop and said clocked latch are connected to a common clock line, said clocked latch being transparent when one logic state is applied to said clock line and wherein the multiplexer connects the output of said clocked latch to the multiplexer output at a transition to the other logic state on said clock line.
Preferably the flip-flop responds to a transition on said clock line from said other state to said one state.
According to a second aspect of the present invention there is provided an integrated circuit comprising an output circuit of the first aspect and further comprising a two-state clock generator connected to said clock line.
According to a third aspect of the present invention there is provided a method of providing an output signal comprising:
providing an input to a first multiplexer input via a clocked latch;
providing an input to a second input of said multiplexer via a flip-flop;
providing a clock signal to clock inputs of said multiplexer, said flip-flop and said clocked latch such that said clocked latch is transparent during one clock state and the multiplexer provides an output from the output of said flip-flop during said one state and the output of the clocked latch as the multiplexer output upon the transition to the other clock state.